Digital logic circuits associated with a memory storage unit can record the transfer of data, commands, or any other information (referred to as “data packets”) with one or more other devices. Data transfer rates can differ between inserting data packets into a memory storage unit and extracting data packets from the memory storage unit.
Asynchronous FIFO (first-in-first-out) circuits provide an important data buffer function for reading and writing operations between two discrete machines of widely differing operating frequency. Asynchronous FIFO circuits are widely used for synchronization of data transfers where transmitter and receiver are working on different frequency and timings.
A FIFO circuit has a data memory that has a plurality of addressable locations. Read and write operations in the FIFO circuit are performed with read and write pointers respectively. The write pointer increments and points to a subsequent address location of the memory storage unit after each data packet insertion into the data memory. The read pointer similarly increments and points to a subsequent address location of the data memory after each data packet extraction from the memory storage unit.
The read and write pointers are compared to track the occupancy of the data memory. Based on the comparison, a signal such as a “memory full” or a “memory empty” is generated to indicate whether to continue with a data packet insertion or extraction operation respectively. If the data memory is full, the data packet insertion operation by an associated circuit will stop its write operation/data packet insertion. Similarly, if the data memory is empty, the associated circuit will stop the read operation/data packet extraction.
In conventional asynchronous FIFO circuits, comparators are used to compare the read and write pointers. The FIFO circuits which have a larger “depth” of the data memory, the sizes of the read pointers, write pointers and comparators increase proportionally. With the increase in comparator size, the insertion and extraction data rates are further reduced. This decreases the operating frequency (frequencies of read clock and write clock) thereby reducing the throughput of the system.
The generation of ‘memory full’ and ‘memory empty’ signals requires synchronization of the write and read pointers in the read and write clock domain respectively. Binary to Gray code and Gray to Binary converters are used to minimize the failures or avoid metastability condition in synchronization of the write and read pointers. Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable; this state is known as metastable state. Metastability state presents potential failure conditions when the read clock and the write clock are very close in operating range.